Paging Simulator
Watch the MMU translate virtual addresses into physical frames
Memory Hierarchy
MMU address translationCPU Virtual Address ↓
▼
MMU
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TLB (Cache)
Hit / Miss ▼
Page Table
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Physical Memory
System Configuration
10Offset Bits
6VPN Bits
64Virtual Pages
64Physical Frames
Virtual Address Translation
Address Breakdown
Page Number
Offset
Enter a virtual address to see the translation steps.
Step-by-Step Translation
Translate an address to see each step of the MMU pipeline.
0 / 0
TLB
Cache| VPN | Frame |
|---|---|
| Empty | |
Page Table
Per-process| VPN | Frame | V | R | D | Perm |
|---|
Physical Memory
64 framesStatistics
0Translations
0TLB Hits
0TLB Misses
0%TLB Hit Rate
0Page Faults